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Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise
Noted) (continued)
( Typical Application Circuit , V CC = V CC_AMP_1 = V CC_AMP_2 = V CC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF
ports are driven from 50 I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P f RF P 500MHz, T C = -40 N C to +85 N C. Typical values
are at maximum gain setting, V CC_ = 5.0V, P IN = -20dBm, f RF = 350MHz, and T C = +25 N C, unless otherwise noted.) (Note 6)
PARAMETER
Attenuation Range
SYMBOL
CONDITIONS
f RF = 350MHz, T C = +25 N C, V CC = 5.0V
MIN
29.5
TYP
33.2
MAX
UNITS
dB
Gain Control Slope
Maximum Gain Control Slope
Insertion Phase Change
Analog control input
Over analog control input range
Over analog control input range
AA_SP = 0, V A_VCTL__
from 2.75V to 0.25V
-13.3
-35.2
17.6
500
dB/V
dB/V
Deg
AA_SP = 1, DAC code
from 11111111 to
00000000, from CS rising
500
Attenuator Response Time
RF settled to
within Q 0.5dB
edge
AA_SP = 0, V A_VCTL__
from 0.25V to 2.75V
500
ns
AA_SP = 1, DAC code
from 00000000 to
11111111, from CS rising
edge
500
Group Delay vs. Control Voltage
Analog Control Input Range
Analog Control Input Impedance
Input Return Loss
Output Return Loss
Over analog control input from 0.25V to
2.75V
50 I source
50 I load
0.25
-0.34
19.2
16.1
16.8
2.75
ns
V
k I
dB
dB
D/A CONVERTER
Number of Bits
8
Bits
Output Voltage
DAC code = 00000000
DAC code = 11111111
2.7
0.35
V
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed
20
MHz
Data-to-Clock Setup Time
Data-to-Clock Hold Time
Clock-to- CS Setup Time
CS Positive Pulse Width
CS Setup Time
Clock Pulse Width
t CS
t CH
t ES
t EW
t EWS
t CW
2
2.5
3
7
3.5
5
ns
ns
ns
ns
ns
ns
_______________________________________________________________________________________
5
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